Huawei’s Atlas 960E SuperPoD Pushes AI Chip Race Toward Cluster Engineering

From accelerator race to system race

Huawei defines a SuperPoD as a computing system in which multiple nodes are tightly coupled through high-speed interconnect and unified memory addressing, making them act more like one logical computer than a loose collection of servers.¹ That framing matters for AI infrastructure readers because large training runs are often constrained not just by peak accelerator FLOPS, but by communication overhead, memory capacity, link latency, power budgets and failure domains.

Huawei says conventional 100,000-NPU training clusters built from 8-NPU servers can spend more than 40% of training time on intra-cluster communication. In company simulations, a 100,000-NPU cluster built from 4,000-NPU-class SuperPoDs delivered a 2.75x Model FLOPs Utilization improvement compared with a cluster composed of 8-NPU servers.¹ Those are vendor claims, not independent benchmark results, but they show the problem Huawei is targeting: improving useful utilization at scale, not only increasing theoretical chip throughput.

The technical bet is that tightly integrated clusters can reduce the penalty of using accelerators that may trail the most advanced imported GPUs on a per-chip basis. Packaging, optical interconnect density and topology design become part of the accelerator architecture.

UnifiedBus and Peerium anchor the claim

Huawei’s Peerium Computing Architecture is the broader systems concept behind the SuperPoD strategy. The company describes it as an architecture designed to make processors at million-scale work as one computer through nested parallelism, unified memory addressing and peer interconnect.² UnifiedBus is the key component: a high-speed bus that Huawei says can connect CPUs, NPUs, memory, SSDs, NICs and switches under a single protocol, enabling peer interconnect across compute, storage and networking.²

TechCrunch similarly framed Huawei’s approach as an attempt to turn hundreds of thousands, and eventually millions, of AI chips into one large computer using Peerium and UnifiedBus.⁴ It also flagged a scale question: Huawei’s current announcement referred to a 4,096-chip Atlas 960 SuperPoD, while earlier discussion had pointed to a larger 15,488-chip design.⁴ For operators, that distinction matters. A roadmap diagram and a deployable fabric are different things, and system size changes the thermal, optical, scheduling and reliability problems.

Huawei says SuperClusters can extend beyond individual SuperPoDs: a two-tier, four-plane Clos architecture can interconnect up to 512,000 NPUs, and a multi-rail topology can reach one million NPUs.¹ The practical question is how much of that scale can be delivered with predictable job placement, acceptable failure recovery and efficient model parallelism.

Near-packaged optics carry the physical-layer story

The Atlas 960E announcement leans heavily on Hi-ONE, Huawei’s near-packaged optics interconnect. Huawei says each Hi-ONE engine delivers 7.2 Tbit/s of transmission capacity and is designed to balance optical, electrical, mechanical, electromagnetic and thermal factors in a dense AI system.¹ AI Magazine summarized the design as using UnifiedBus and Hi-ONE to coordinate NPUs over high-speed interconnect, with NPO reducing the need for separate optical modules and helping scale SuperPoD fabrics.⁷

The engineering significance is that AI cluster performance increasingly depends on the physical layer. At thousands of accelerators, pluggable optics, cables, switch radix, retimers and power overhead are not secondary details. They define how much of the accelerator pool can be used efficiently. Huawei’s claimed 550 kW power reduction is therefore more than an energy metric. It is also a density and reliability metric, because every removed optical module eliminates a potential heat source and failure point.¹

Inference depends on storage, not just compute

Huawei also linked the SuperPoD announcement to OceanStor M900, a context-memory storage system designed for inference workloads where KV cache can dominate memory demand. The company says M900 uses UnifiedBus to build a PB-scale shared KV-cache pool with one-hop NPU-to-SSD access, extending cache beyond on-chip memory and DRAM to SSDs.³

The claimed specifications target long-context and agentic inference: 64 PB of cluster capacity, 40 TB/s of aggregate access bandwidth, latency reduced to 60 microseconds and doubled token throughput in typical AI programming scenarios.³ Huawei also says the storage layer can halve time to first token and extend SSD endurance by 16x through KV-aware adaptive placement.³

This is the clearest example of the cluster-level thesis. For inference, accelerator TOPS or FLOPS alone do not determine throughput. The system must keep KV cache available, reduce recomputation, avoid CPU forwarding where possible and maintain high cache hit rates as sessions lengthen. Huawei is treating storage as part of the accelerator fabric rather than an external subsystem.

The chip roadmap still matters

Huawei said Ascend 960DT will be available in the first quarter of 2027 and Ascend 960PR in the third quarter of 2027. It also laid out plans for Ascend 970 in 2028 and Ascend 980 in 2029, saying each generation should continue improving compute, memory bandwidth, memory capacity and interconnect bandwidth.¹ AP also reported the 2028 and 2029 roadmap for Ascend 970 and 980, with expectations of significant computing-power gains.⁸

The roadmap matters because cluster engineering cannot fully offset weak silicon indefinitely. Memory bandwidth per accelerator, HBM capacity, interconnect endpoints and software support all compound at scale. But Huawei’s September 17 announcements suggest a strategy of shifting the comparison from “which single chip is fastest” to “which infrastructure stack can expose more usable compute to models.”

That is the core engineering takeaway. Huawei is packaging domestic accelerators into larger AI systems by combining NPUs, near-packaged optics, a unified interconnect protocol, shared addressing and inference-oriented storage. Whether the claims hold up in production will depend on independent workload results, software maturity and real deployment reliability. But the direction is clear: in the next phase of AI infrastructure competition, process-node parity may be only one variable among many.